1. Field of the Invention
The present invention relates to protection circuits for the terminals of an integrated circuit device, and more specifically to a protection circuit for a terminal of a power supply line of the pulse type.
2. Description of Related Art
Conventional MOS integrated circuits, and in general low voltage supply portions of mixed technology integrated devices, can suffer serious damage from electrostatic discharges (ESDs) to any device terminal. It has been recognized that the terminals of an integrated circuit device are likely to incidentally contact electrically-charged objects during both fabrication and mounting to a circuit assembly. Such a contact can introduce an ESD and create potential differences of considerable magnitude between the semiconductor substrate of the integrated circuit and the gate electrodes of the input transistors or the drain regions of the output transistors.
With respect to an input transistor, if the potential difference exceeds the dielectric strength threshold of the gate insulation, the transistor is made unusable by the ESD that breaks down the gate insulation. A similar destructive effect occurs in an output transistor if the potential difference exceeds the reverse breakdown threshold of the drain junction. As an example, a CMOS integrated circuit fabricated with 1.2 .mu.m technology (i.e., with minimum gate dimensions of 1.2 .mu.m), has a breakdown voltage of approximately 12-14V for input transistors and approximately 12V for output transistors.
There are several conventional ways for protecting the input, output, and supply terminals of an integrated circuit from electrostatic discharges. Generally, protectors using lateral bipolar transistors are used for this purpose. One example of a conventional protection device that is specially adapted for monolithic integration to a MOS-type integrated circuit is described in Italian Patent Application No. 26063 A/80 by the present applicant. The disclosed device has a lateral NPN transistor whose emitter and collector are doped with N-type impurities simultaneously and identically with the source and drain regions of the IGFETs in the MOS circuit to be protected. The base of the NPN transistor is made inaccessible and is heavily and deeply doped with acceptor ions (i.e., P-type impurities) through ion implantation.
An improved version of this protection structure is disclosed in Italian Patent Application No. 23077 A/85 by the present applicant. The protection circuit includes two lateral bipolar transistors that have both emitter terminals connected to a ground terminal, one collector terminal connected to the input terminal of the circuit, and another collector terminal connected to the gate terminals of the IGFETs. A diffused resistor R' interconnects the collectors of the two lateral transistors. Further, the base width of the first transistor and the impurity concentration in the bases of both transistors are selected so as to hold the negative resistance phenomena trigger voltage of the first transistor and the breakdown voltage of the second transistor at a lower value than the breakdown voltage of the gate isolation oxides and the bipolar junctions of the elements in the integrated circuit. Further, these values are chosen so as to hold the sustaining voltage of the first transistor at a higher value than the integrated circuit supply voltage.
Another simple, yet effective conventional ESD protection circuit is formed by a bipolar transistor connected between an integrated circuit terminal and ground. The base and emitter of the transistor are short circuited so that the transistor exhibits a current/voltage characteristic of the bistable type between a high-impedance, high-voltage state (designated BVcbo in the pertinent art) and a low-impedance, low-voltage state (designated BVcer). The transistor operates in the high-impedance, high-voltage mode during normal circuit operation without affecting the circuit. On the occurrence of an ESD, the transistor is forced into the low-impedance, low-voltage mode and thus opens a path to ground for the ESD pulse.
The effectiveness of protectors employing bipolar transistors is much lower in protecting a supply terminal or line. In fact, the BVcbo and BVcer may have statistic process variations that cause inconsistent actual values for a terminal or line that is at the maximum potential provided in the integrated circuit. Additionally, voltage noise on a supply line can accidentally turn on the bipolar protection transistor and clamp the supply voltage on BVcer, which is usually much lower than the voltage needed to power the circuit. This can cause a circuit malfunction and can even cause permanent damage when a large DC current flows through the circuit.
An ESD protection circuit for use on a power supply terminal or line is disclosed in European Patent Application No. 96-830664.7 by the present applicant. As shown in FIG. 1, the disclosed protection circuit includes a first field-effect transistor M1 whose drain terminal is connected to the supply line Vdd and whose gate and source terminals are connected to ground GND through first and second resistors R1 and R2, respectively. Additionally, a second field-effect transistor M2 is connected between ground and the supply line, with the gate terminal of the second transistor M2 connected to the source terminal of the first transistor M1. A capacitor C is optionally connected between the gate terminal and the drain terminal of the first transistor M1. In the absence of the capacitor, the protective function is ensured by the intrinsic capacitance between the gate and the drain of the first transistor.
The protection circuit of FIG. 1 provides a dynamic circuit that becomes activated only by transient conditions and that reveals no dangerous latch-up side actions. However, if a pulse-type power supply (i.e., chopper-type power supply) is used, the conventional protection circuits described above cannot provide effective protection for the supply line whenever the switching transistors of the supply have comparable rates (d voltage/d time) to the electrostatic discharge transients. In particular, the conventional protection circuits fail to detect electrical transients that coincidentally happen to be similar to those from the switching transistors. Thus, the circuit can malfunction and possibly even be damaged.